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tests/avocado: riscv: Enable 32-bit Spike OpenSBI boot testing

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The 32-bit Spike boot issue has been fixed in the OpenSBI v1.3.
Let's enable the 32-bit Spike OpenSBI boot testing.

Signed-off-by: Bin Meng <bmeng@tinylab.org>
Message-Id: <20230630160717.843044-2-bmeng@tinylab.org>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2023-06-30 23:39:23 +08:00 committed by Alistair Francis
parent aa903cf313
commit 11b937b652
1 changed files with 0 additions and 2 deletions
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2
tests/avocado/riscv_opensbi.py
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@ -6,7 +6,6 @@
# later. See the COPYING file in the top-level directory. # later. See the COPYING file in the top-level directory.
from avocado_qemu import QemuSystemTest from avocado_qemu import QemuSystemTest
from avocado import skip
from avocado_qemu import wait_for_console_pattern from avocado_qemu import wait_for_console_pattern
class RiscvOpenSBI(QemuSystemTest): class RiscvOpenSBI(QemuSystemTest):
@ -21,7 +20,6 @@ def boot_opensbi(self):
wait_for_console_pattern(self, 'Platform Name') wait_for_console_pattern(self, 'Platform Name')
wait_for_console_pattern(self, 'Boot HART MEDELEG') wait_for_console_pattern(self, 'Boot HART MEDELEG')
@skip("requires OpenSBI fix to work")
def test_riscv32_spike(self): def test_riscv32_spike(self):
""" """
:avocado: tags=arch:riscv32 :avocado: tags=arch:riscv32