From 2e6a646d7b1304d9106baad73c655132e2736c6c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 4 Sep 2019 12:30:45 -0700 Subject: [PATCH] target/arm: Convert T16 adjust sp (immediate) Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20190904193059.26202-56-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/t16.decode | 9 +++++++++ target/arm/translate.c | 15 ++------------- 2 files changed, 11 insertions(+), 13 deletions(-) diff --git a/target/arm/t16.decode b/target/arm/t16.decode index 5a570484e3..b425b86795 100644 --- a/target/arm/t16.decode +++ b/target/arm/t16.decode @@ -156,6 +156,15 @@ ADD_rrri 0100 0100 . .... ... @addsub_2h s=0 CMP_xrri 0100 0101 . .... ... @addsub_2h s=1 MOV_rxri 0100 0110 . .... ... @addsub_2h s=0 +# Adjust SP (immediate) + +%imm7_0x4 0:7 !function=times_4 +@addsub_sp_i .... .... . ....... \ + &s_rri_rot s=0 rd=13 rn=13 rot=0 imm=%imm7_0x4 + +ADD_rri 1011 0000 0 ....... @addsub_sp_i +SUB_rri 1011 0000 1 ....... @addsub_sp_i + # Branch and exchange @branchr .... .... . rm:4 ... &r diff --git a/target/arm/translate.c b/target/arm/translate.c index 73c8863134..8399a2c1f6 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -10765,19 +10765,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn) /* misc */ op = (insn >> 8) & 0xf; switch (op) { - case 0: - /* - * 0b1011_0000_xxxx_xxxx - * - ADD (SP plus immediate) - * - SUB (SP minus immediate) - */ - tmp = load_reg(s, 13); - val = (insn & 0x7f) * 4; - if (insn & (1 << 7)) - val = -(int32_t)val; - tcg_gen_addi_i32(tmp, tmp, val); - store_sp_checked(s, tmp); - break; + case 0: /* add/sub (sp, immediate), in decodetree */ + goto illegal_op; case 2: /* sign/zero extend. */ ARCH(6);