softmmu/physmem: Introduce MemTxAttrs::memory field and MEMTX_ACCESS_ERROR
Add the 'memory' bit to the memory attributes to restrict bus controller accesses to memories. Introduce flatview_access_allowed() to check bus permission before running any bus transaction. Have read/write accessors return MEMTX_ACCESS_ERROR if an access is restricted. There is no change for the default case where 'memory' is not set. Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-Id: <20211215182421.418374-4-philmd@redhat.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> [thuth: Replaced MEMTX_BUS_ERROR with MEMTX_ACCESS_ERROR, remove "inline"] Signed-off-by: Thomas Huth <thuth@redhat.com>
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@ -35,6 +35,14 @@ typedef struct MemTxAttrs {
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unsigned int secure:1;
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unsigned int secure:1;
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/* Memory access is usermode (unprivileged) */
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/* Memory access is usermode (unprivileged) */
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unsigned int user:1;
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unsigned int user:1;
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/*
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* Bus interconnect and peripherals can access anything (memories,
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* devices) by default. By setting the 'memory' bit, bus transaction
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* are restricted to "normal" memories (per the AMBA documentation)
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* versus devices. Access to devices will be logged and rejected
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* (see MEMTX_ACCESS_ERROR).
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*/
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unsigned int memory:1;
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/* Requester ID (for MSI for example) */
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/* Requester ID (for MSI for example) */
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unsigned int requester_id:16;
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unsigned int requester_id:16;
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/* Invert endianness for this page */
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/* Invert endianness for this page */
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@ -66,6 +74,7 @@ typedef struct MemTxAttrs {
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#define MEMTX_OK 0
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#define MEMTX_OK 0
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#define MEMTX_ERROR (1U << 0) /* device returned an error */
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#define MEMTX_ERROR (1U << 0) /* device returned an error */
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#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
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#define MEMTX_DECODE_ERROR (1U << 1) /* nothing at that address */
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#define MEMTX_ACCESS_ERROR (1U << 2) /* access denied */
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typedef uint32_t MemTxResult;
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typedef uint32_t MemTxResult;
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#endif
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#endif
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@ -42,6 +42,7 @@
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#include "qemu/config-file.h"
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#include "qemu/config-file.h"
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#include "qemu/error-report.h"
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#include "qemu/error-report.h"
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#include "qemu/qemu-print.h"
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#include "qemu/qemu-print.h"
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#include "qemu/log.h"
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#include "qemu/memalign.h"
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#include "qemu/memalign.h"
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#include "exec/memory.h"
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#include "exec/memory.h"
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#include "exec/ioport.h"
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#include "exec/ioport.h"
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@ -2760,6 +2761,33 @@ static bool prepare_mmio_access(MemoryRegion *mr)
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return release_lock;
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return release_lock;
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}
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}
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/**
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* flatview_access_allowed
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* @mr: #MemoryRegion to be accessed
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* @attrs: memory transaction attributes
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* @addr: address within that memory region
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* @len: the number of bytes to access
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*
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* Check if a memory transaction is allowed.
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*
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* Returns: true if transaction is allowed, false if denied.
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*/
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static bool flatview_access_allowed(MemoryRegion *mr, MemTxAttrs attrs,
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hwaddr addr, hwaddr len)
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{
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if (likely(!attrs.memory)) {
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return true;
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}
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if (memory_region_is_ram(mr)) {
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return true;
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}
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid access to non-RAM device at "
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"addr 0x%" HWADDR_PRIX ", size %" HWADDR_PRIu ", "
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"region '%s'\n", addr, len, memory_region_name(mr));
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return false;
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}
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/* Called within RCU critical section. */
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/* Called within RCU critical section. */
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static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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MemTxAttrs attrs,
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MemTxAttrs attrs,
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@ -2774,7 +2802,10 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
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const uint8_t *buf = ptr;
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const uint8_t *buf = ptr;
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for (;;) {
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for (;;) {
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if (!memory_access_is_direct(mr, true)) {
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if (!flatview_access_allowed(mr, attrs, addr1, l)) {
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result |= MEMTX_ACCESS_ERROR;
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/* Keep going. */
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} else if (!memory_access_is_direct(mr, true)) {
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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l = memory_access_size(mr, l, addr1);
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/* XXX: could force current_cpu to NULL to avoid
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/* XXX: could force current_cpu to NULL to avoid
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@ -2819,6 +2850,9 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
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l = len;
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l = len;
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mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
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mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
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if (!flatview_access_allowed(mr, attrs, addr, len)) {
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return MEMTX_ACCESS_ERROR;
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}
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return flatview_write_continue(fv, addr, attrs, buf, len,
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return flatview_write_continue(fv, addr, attrs, buf, len,
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addr1, l, mr);
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addr1, l, mr);
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}
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}
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@ -2837,7 +2871,10 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
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fuzz_dma_read_cb(addr, len, mr);
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fuzz_dma_read_cb(addr, len, mr);
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for (;;) {
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for (;;) {
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if (!memory_access_is_direct(mr, false)) {
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if (!flatview_access_allowed(mr, attrs, addr1, l)) {
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result |= MEMTX_ACCESS_ERROR;
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/* Keep going. */
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} else if (!memory_access_is_direct(mr, false)) {
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/* I/O case */
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/* I/O case */
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release_lock |= prepare_mmio_access(mr);
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release_lock |= prepare_mmio_access(mr);
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l = memory_access_size(mr, l, addr1);
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l = memory_access_size(mr, l, addr1);
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@ -2880,6 +2917,9 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
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l = len;
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l = len;
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mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
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mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
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if (!flatview_access_allowed(mr, attrs, addr, len)) {
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return MEMTX_ACCESS_ERROR;
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}
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return flatview_read_continue(fv, addr, attrs, buf, len,
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return flatview_read_continue(fv, addr, attrs, buf, len,
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addr1, l, mr);
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addr1, l, mr);
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}
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}
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