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ppc/ppc405: QOM'ify EBC

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EBC is currently modeled as a DCR device. Also drop the ppc405_ebc_init()
helper and adapt the sam460ex machine.

Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <51a0769ab605c5158f4f2f1c896725d5fe7a073b.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
This commit is contained in:
Cédric Le Goater 2022-08-17 17:08:25 +02:00 committed by Daniel Henrique Barboza
parent 82c86e304a
commit 415a6333d4
3 changed files with 50 additions and 31 deletions
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17
hw/ppc/ppc405.h
View file

@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t {
uint32_t bi_iic_fast[2];
};
/* Peripheral controller */
#define TYPE_PPC405_EBC "ppc405-ebc"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405EbcState, PPC405_EBC);
struct Ppc405EbcState {
Ppc4xxDcrDeviceState parent_obj;
uint32_t addr;
uint32_t bcr[8];
uint32_t bap[8];
uint32_t bear;
uint32_t besr0;
uint32_t besr1;
uint32_t cfg;
};
/* DMA controller */
#define TYPE_PPC405_DMA "ppc405-dma"
OBJECT_DECLARE_SIMPLE_TYPE(Ppc405DmaState, PPC405_DMA);
@ -192,12 +207,12 @@ struct Ppc405SoCState {
Ppc405OcmState ocm;
Ppc405GpioState gpio;
Ppc405DmaState dma;
Ppc405EbcState ebc;
};
/* PowerPC 405 core */
ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size);
void ppc4xx_plb_init(CPUPPCState *env);
void ppc405_ebc_init(CPUPPCState *env);
#endif /* PPC405_H */

60
hw/ppc/ppc405_uc.c
View file

@ -393,28 +393,16 @@ static void ppc4xx_opba_init(hwaddr base)
/*****************************************************************************/
/* Peripheral controller */
typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
struct ppc4xx_ebc_t {
uint32_t addr;
uint32_t bcr[8];
uint32_t bap[8];
uint32_t bear;
uint32_t besr0;
uint32_t besr1;
uint32_t cfg;
};
enum {
EBC0_CFGADDR = 0x012,
EBC0_CFGDATA = 0x013,
};
static uint32_t dcr_read_ebc (void *opaque, int dcrn)
static uint32_t dcr_read_ebc(void *opaque, int dcrn)
{
ppc4xx_ebc_t *ebc;
Ppc405EbcState *ebc = opaque;
uint32_t ret;
ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ret = ebc->addr;
@ -494,11 +482,10 @@ static uint32_t dcr_read_ebc (void *opaque, int dcrn)
return ret;
}
static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
static void dcr_write_ebc(void *opaque, int dcrn, uint32_t val)
{
ppc4xx_ebc_t *ebc;
Ppc405EbcState *ebc = opaque;
ebc = opaque;
switch (dcrn) {
case EBC0_CFGADDR:
ebc->addr = val;
@ -554,12 +541,11 @@ static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
}
}
static void ebc_reset (void *opaque)
static void ppc405_ebc_reset(DeviceState *dev)
{
ppc4xx_ebc_t *ebc;
Ppc405EbcState *ebc = PPC405_EBC(dev);
int i;
ebc = opaque;
ebc->addr = 0x00000000;
ebc->bap[0] = 0x7F8FFE80;
ebc->bcr[0] = 0xFFE28000;
@ -572,16 +558,23 @@ static void ebc_reset (void *opaque)
ebc->cfg = 0x80400000;
}
void ppc405_ebc_init(CPUPPCState *env)
static void ppc405_ebc_realize(DeviceState *dev, Error **errp)
{
ppc4xx_ebc_t *ebc;
Ppc405EbcState *ebc = PPC405_EBC(dev);
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
ebc = g_new0(ppc4xx_ebc_t, 1);
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc_dcr_register(env, EBC0_CFGDATA,
ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc4xx_dcr_register(dcr, EBC0_CFGADDR, ebc, &dcr_read_ebc, &dcr_write_ebc);
ppc4xx_dcr_register(dcr, EBC0_CFGDATA, ebc, &dcr_read_ebc, &dcr_write_ebc);
}
static void ppc405_ebc_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
dc->realize = ppc405_ebc_realize;
dc->reset = ppc405_ebc_reset;
/* Reason: only works as function of a ppc4xx SoC */
dc->user_creatable = false;
}
/*****************************************************************************/
@ -1378,6 +1371,8 @@ static void ppc405_soc_instance_init(Object *obj)
object_initialize_child(obj, "gpio", &s->gpio, TYPE_PPC405_GPIO);
object_initialize_child(obj, "dma", &s->dma, TYPE_PPC405_DMA);
object_initialize_child(obj, "ebc", &s->ebc, TYPE_PPC405_EBC);
}
static void ppc405_reset(void *opaque)
@ -1444,7 +1439,9 @@ static void ppc405_soc_realize(DeviceState *dev, Error **errp)
s->do_dram_init);
/* External bus controller */
ppc405_ebc_init(env);
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->ebc), &s->cpu, errp)) {
return;
}
/* DMA controller */
if (!ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(&s->dma), &s->cpu, errp)) {
@ -1526,6 +1523,11 @@ static void ppc405_soc_class_init(ObjectClass *oc, void *data)
static const TypeInfo ppc405_types[] = {
{
.name = TYPE_PPC405_EBC,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405EbcState),
.class_init = ppc405_ebc_class_init,
}, {
.name = TYPE_PPC405_DMA,
.parent = TYPE_PPC4xx_DCR_DEVICE,
.instance_size = sizeof(Ppc405DmaState),

4
hw/ppc/sam460ex.c
View file

@ -371,7 +371,9 @@ static void sam460ex_init(MachineState *machine)
qdev_get_gpio_in(uic[0], 3));
/* External bus controller */
ppc405_ebc_init(env);
dev = qdev_new(TYPE_PPC405_EBC);
ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(dev), cpu, &error_fatal);
object_unref(OBJECT(dev));
/* CPR */
ppc4xx_cpr_init(env);