hw/mips/bootloader: Implement nanoMIPS SW opcode generator
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20221211204533.85359-4-philmd@linaro.org>
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@ -143,10 +143,28 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
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bl_gen_i_type(p, 0x0d, rs, rt, imm);
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bl_gen_i_type(p, 0x0d, rs, rt, imm);
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}
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}
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static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
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{
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uint32_t insn = 0;
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assert(extract32(ofs12, 0, 12) == ofs12);
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insn = deposit32(insn, 26, 6, 0b100001);
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insn = deposit32(insn, 21, 5, rt);
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insn = deposit32(insn, 16, 5, rs);
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insn = deposit32(insn, 12, 4, 0b1001);
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insn = deposit32(insn, 0, 12, ofs12);
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st_nm32_p(ptr, insn);
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}
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static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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{
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if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
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bl_gen_sw_nm(p, rt, base, offset);
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} else {
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bl_gen_i_type(p, 0x2b, base, rt, offset);
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bl_gen_i_type(p, 0x2b, base, rt, offset);
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}
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}
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}
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static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
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{
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{
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