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hw/mips/bootloader: Implement nanoMIPS SW opcode generator

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Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20221211204533.85359-4-philmd@linaro.org>
This commit is contained in:
Philippe Mathieu-Daudé 2022-12-11 18:33:52 +01:00
parent cf386ca8ab
commit 73be38cbe3
1 changed files with 19 additions and 1 deletions
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18
hw/mips/bootloader.c
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@ -143,10 +143,28 @@ static void bl_gen_ori(void **p, bl_reg rt, bl_reg rs, uint16_t imm)
bl_gen_i_type(p, 0x0d, rs, rt, imm);
}
static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, uint16_t ofs12)
{
uint32_t insn = 0;
assert(extract32(ofs12, 0, 12) == ofs12);
insn = deposit32(insn, 26, 6, 0b100001);
insn = deposit32(insn, 21, 5, rt);
insn = deposit32(insn, 16, 5, rs);
insn = deposit32(insn, 12, 4, 0b1001);
insn = deposit32(insn, 0, 12, ofs12);
st_nm32_p(ptr, insn);
}
static void bl_gen_sw(void **p, bl_reg rt, uint8_t base, uint16_t offset)
{
if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
bl_gen_sw_nm(p, rt, base, offset);
} else {
bl_gen_i_type(p, 0x2b, base, rt, offset);
}
}
static void bl_gen_sd(void **p, bl_reg rt, uint8_t base, uint16_t offset)
{