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target/riscv: smstateen check for fcsr

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Implement the s/h/mstateen.fcsr bit as defined in the smstateen spec
and check for it when accessing the fcsr register and its fields.

Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Reviewed-by: Weiwei Li <liweiwei@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230518175058.2772506-2-mchitale@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Mayuresh Chitale 2023-05-18 23:20:56 +05:30 committed by Alistair Francis
parent 30a0d77622
commit 9514fc72d0
1 changed files with 15 additions and 0 deletions
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15
target/riscv/csr.c
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@ -82,6 +82,10 @@ static RISCVException fs(CPURISCVState *env, int csrno)
!riscv_cpu_cfg(env)->ext_zfinx) {
return RISCV_EXCP_ILLEGAL_INST;
}
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return smstateen_acc_ok(env, 0, SMSTATEEN0_FCSR);
}
#endif
return RISCV_EXCP_NONE;
}
@ -2104,6 +2108,9 @@ static RISCVException write_mstateen0(CPURISCVState *env, int csrno,
target_ulong new_val)
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
if (!riscv_has_ext(env, RVF)) {
wr_mask |= SMSTATEEN0_FCSR;
}
return write_mstateen(env, csrno, wr_mask, new_val);
}
@ -2177,6 +2184,10 @@ static RISCVException write_hstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
if (!riscv_has_ext(env, RVF)) {
wr_mask |= SMSTATEEN0_FCSR;
}
return write_hstateen(env, csrno, wr_mask, new_val);
}
@ -2263,6 +2274,10 @@ static RISCVException write_sstateen0(CPURISCVState *env, int csrno,
{
uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG;
if (!riscv_has_ext(env, RVF)) {
wr_mask |= SMSTATEEN0_FCSR;
}
return write_sstateen(env, csrno, wr_mask, new_val);
}