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hw/misc: Add PWRON STRAP bit fields in GCR module

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Similar to the Aspeed code in include/misc/aspeed_scu.h, we define
the PWRON STRAP fields in their corresponding module for NPCM7XX.

Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture <venture@google.com>
Message-id: 20220411165842.3912945-2-wuhaotsh@google.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Hao Wu 2022-04-11 09:58:41 -07:00 committed by Peter Maydell
parent 011301736b
commit c3e9e73a83
1 changed files with 30 additions and 0 deletions
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30
include/hw/misc/npcm7xx_gcr.h
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@ -19,6 +19,36 @@
#include "exec/memory.h"
#include "hw/sysbus.h"
/*
* NPCM7XX PWRON STRAP bit fields
* 12: SPI0 powered by VSBV3 at 1.8V
* 11: System flash attached to BMC
* 10: BSP alternative pins.
* 9:8: Flash UART command route enabled.
* 7: Security enabled.
* 6: HI-Z state control.
* 5: ECC disabled.
* 4: Reserved
* 3: JTAG2 enabled.
* 2:0: CPU and DRAM clock frequency.
*/
#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12)
#define NPCM7XX_PWRON_STRAP_SFAB BIT(11)
#define NPCM7XX_PWRON_STRAP_BSPA BIT(10)
#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8)
#define FUP_NORM_UART2 3
#define FUP_PROG_UART3 2
#define FUP_PROG_UART2 1
#define FUP_NORM_UART3 0
#define NPCM7XX_PWRON_STRAP_SECEN BIT(7)
#define NPCM7XX_PWRON_STRAP_HIZ BIT(6)
#define NPCM7XX_PWRON_STRAP_ECC BIT(5)
#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4)
#define NPCM7XX_PWRON_STRAP_J2EN BIT(3)
#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x)
#define CKFRQ_SKIPINIT 0x000
#define CKFRQ_DEFAULT 0x111
/*
* Number of registers in our device state structure. Don't change this without
* incrementing the version_id in the vmstate.