target/tricore: Fix RCPW/RRPW_INSERT insns for width = 0
we would crash if width was 0 for these insns, as tcg_gen_deposit() is undefined for that case. For TriCore, width = 0 is a mov from the src reg to the dst reg, so we special case this here. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Message-ID: <20230828112651.522058-9-kbastian@mail.uni-paderborn.de> (cherry picked from commit 23fa6f56b33f8fddf86ba4d027fb7d3081440cd9) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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@ -5317,8 +5317,11 @@ static void decode_rcpw_insert(DisasContext *ctx)
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}
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}
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break;
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break;
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case OPC2_32_RCPW_INSERT:
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case OPC2_32_RCPW_INSERT:
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/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
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if (width == 0) {
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tcg_gen_mov_tl(cpu_gpr_d[r2], cpu_gpr_d[r1]);
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/* if pos + width > 32 undefined result */
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/* if pos + width > 32 undefined result */
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if (pos + width <= 32) {
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} else if (pos + width <= 32) {
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temp = tcg_constant_i32(const4);
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temp = tcg_constant_i32(const4);
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tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
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tcg_gen_deposit_tl(cpu_gpr_d[r2], cpu_gpr_d[r1], temp, pos, width);
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}
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}
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@ -6558,7 +6561,10 @@ static void decode_rrpw_extract_insert(DisasContext *ctx)
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break;
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break;
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case OPC2_32_RRPW_INSERT:
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case OPC2_32_RRPW_INSERT:
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if (pos + width <= 32) {
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/* tcg_gen_deposit_tl() does not handle the case of width = 0 */
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if (width == 0) {
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tcg_gen_mov_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]);
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} else if (pos + width <= 32) {
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tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
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tcg_gen_deposit_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], cpu_gpr_d[r2],
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pos, width);
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pos, width);
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}
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}
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@ -161,6 +161,21 @@ test_ ## num: \
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insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
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insn DREG_CALC_RESULT, DREG_RS1, imm1, DREG_RS2, imm2; \
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)
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)
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#define TEST_D_DDII(insn, num, result, rs1, rs2, imm1, imm2) \
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TEST_CASE(num, DREG_CALC_RESULT, result, \
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LI(DREG_RS1, rs1); \
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LI(DREG_RS2, rs2); \
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rstv; \
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insn DREG_CALC_RESULT, DREG_RS1, DREG_RS2, imm1, imm2; \
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)
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#define TEST_D_DIII(insn, num, result, rs1, imm1, imm2, imm3)\
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TEST_CASE(num, DREG_CALC_RESULT, result, \
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LI(DREG_RS1, rs1); \
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rstv; \
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insn DREG_CALC_RESULT, DREG_RS1, imm1, imm2, imm3; \
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)
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#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
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#define TEST_E_ED(insn, num, res_hi, res_lo, rs1_hi, rs1_lo, rs2) \
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TEST_CASE_E(num, res_lo, res_hi, \
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TEST_CASE_E(num, res_lo, res_hi, \
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LI(EREG_RS1_LO, rs1_lo); \
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LI(EREG_RS1_LO, rs1_lo); \
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@ -6,4 +6,13 @@ _start:
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# | | | | | | |
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# | | | | | | |
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TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
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TEST_D_DIDI(insert, 1, 0x7fffffff, 0xffffffff, 0xa, 0x10, 0x8)
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# insn num result rs1 imm1 imm2 imm3
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# | | | | | | |
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TEST_D_DIII(insert, 2, 0xd38fe370, 0xd38fe370, 0x4, 0x4 , 0x0)
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TEST_D_DIII(insert, 3, 0xd38fe374, 0xd38fe370, 0x4, 0x0 , 0x4)
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# insn num result rs1 rs2 pos width
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# | | | | | | |
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TEST_D_DDII(insert, 4, 0x03c1e53c, 0x03c1e53c, 0x45821385, 0x7 ,0x0)
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TEST_PASSFAIL
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TEST_PASSFAIL
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