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target/mips: Fix MSA BZ/BNZ opcodes displacement

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The PC offset is *signed*.

Cc: qemu-stable@nongnu.org
Reported-by: Sergey Evlashev <vectorchiefrocks@gmail.com>
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1624
Fixes: c7a9ef7517 ("target/mips: Introduce decode tree bindings for MSA ASE")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914085807.12241-1-philmd@linaro.org>
(cherry picked from commit 04591b3ddd9a96b9298a1dd437a6464ab55e62ee)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
This commit is contained in:
Philippe Mathieu-Daudé 2023-09-14 10:39:37 +02:00 committed by Michael Tokarev
parent 801b7e4390
commit f68a36b7c4
1 changed files with 2 additions and 2 deletions
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4
target/mips/tcg/msa.decode
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@ -31,8 +31,8 @@
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
@ldst ...... sa:s10 ws:5 wd:5 .... df:2 &msa_i
@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:16 &msa_bz
@bz_v ...... ... .. wt:5 sa:s16 &msa_bz df=3
@bz ...... ... df:2 wt:5 sa:s16 &msa_bz
@elm_df ...... .... ...... ws:5 wd:5 ...... &msa_elm_df df=%elm_df n=%elm_n
@elm ...... .......... ws:5 wd:5 ...... &msa_elm
@vec ...... ..... wt:5 ws:5 wd:5 ...... &msa_r df=0