qemu/hw/pci-bridge
Peter Maydell 503d86dd66 hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table()
In build_cdat_table() we do:
 *cdat_table = g_malloc0(sizeof(*cdat_table) * CXL_USP_CDAT_NUM_ENTRIES);
This is wrong because:
 - cdat_table has type CDATSubHeader ***
 - so *cdat_table has type CDATSubHeader **
 - so the array we're allocating here should be items of type CDATSubHeader *
 - but we pass sizeof(*cdat_table), which is sizeof(CDATSubHeader **),
   implying that we're allocating an array of CDATSubHeader **

It happens that sizeof(CDATSubHeader **) == sizeof(CDATSubHeader *)
so nothing blows up, but this should be sizeof(**cdat_table).

Avoid this excessively hard-to-understand code by using
g_new0() instead, which will do the type checking for us.
While we're here, we can drop the useless check against failure,
as g_malloc0() and g_new0() never fail.

This fixes Coverity issue CID 1508120.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20230718101327.1111374-1-peter.maydell@linaro.org>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
2023-08-03 16:06:49 -04:00
..
cxl_downstream.c hw/pci-bridge/cxl_downstream: Fix type naming mismatch 2023-03-02 19:13:52 -05:00
cxl_root_port.c hw/pci-bridge/cxl_root_port: Wire up MSI 2023-03-07 12:39:00 -05:00
cxl_upstream.c hw/pci-bridge/cxl_upstream.c: Use g_new0() in build_cdat_table() 2023-08-03 16:06:49 -04:00
gen_pcie_root_port.c pci: acpi hotplug: rename x-native-hotplug to x-do-not-expose-native-hotplug-cap 2023-01-28 06:21:29 -05:00
i82801b11.c hw: Move ich9.h to southbridge/ 2023-02-27 22:29:01 +01:00
ioh3420.c
Kconfig hw/pci-bridge: make building pcie-to-pci bridge configurable 2023-05-19 10:30:46 -04:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
pci_bridge_dev.c pci_bridge: remove whitespace 2023-01-28 06:21:29 -05:00
pci_expander_bridge.c hw/pci-bridge: Make PCIe and CXL PXB Devices inherit from TYPE_PXB_DEV 2023-04-24 22:56:55 -04:00
pci_expander_bridge_stubs.c pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. 2022-06-09 19:32:49 -04:00
pcie_pci_bridge.c pci: drop redundant PCIDeviceClass::is_bridge field 2022-12-21 07:32:24 -05:00
pcie_root_port.c pci: drop redundant PCIDeviceClass::is_bridge field 2022-12-21 07:32:24 -05:00
simba.c pci: drop redundant PCIDeviceClass::is_bridge field 2022-12-21 07:32:24 -05:00
xio3130_downstream.c pci: drop redundant PCIDeviceClass::is_bridge field 2022-12-21 07:32:24 -05:00
xio3130_upstream.c pci: drop redundant PCIDeviceClass::is_bridge field 2022-12-21 07:32:24 -05:00