qemu/tcg/aarch64
Richard Henderson d46259c037 tcg: Split out tcg-target-reg-bits.h
Often, the only thing we need to know about the TCG host
is the register size.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2023-06-05 12:04:28 -07:00
..
tcg-target-con-set.h tcg/aarch64: Support 128-bit load/store 2023-05-30 09:51:11 -07:00
tcg-target-con-str.h tcg/aarch64: Simplify constraints on qemu_ld/st 2023-05-30 09:51:11 -07:00
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2023-06-05 12:04:28 -07:00
tcg-target.c.inc tcg: Add tlb_fast_offset to TCGContext 2023-06-05 12:04:28 -07:00
tcg-target.h tcg: Remove TCG_TARGET_TLB_DISPLACEMENT_BITS 2023-05-30 09:51:51 -07:00
tcg-target.opc.h tcg/aarch64: Implement INDEX_op_rotl{i,v}_vec 2020-06-02 08:42:37 -07:00