60c7dd22e1
When ADCX is followed by ADOX or vice versa, the second instruction's
carry comes from EFLAGS and the condition codes use the CC_OP_ADCOX
operation. Retrieving the carry from EFLAGS is handled by this bit
of gen_ADCOX:
tcg_gen_extract_tl(carry_in, cpu_cc_src,
ctz32(cc_op == CC_OP_ADCX ? CC_C : CC_O), 1);
Unfortunately, in this case cc_op has been overwritten by the previous
"if" statement to CC_OP_ADCOX. This works by chance when the first
instruction is ADCX; however, if the first instruction is ADOX,
ADCX will incorrectly take its carry from OF instead of CF.
Fix by moving the computation of the new cc_op at the end of the function.
The included exhaustive test case fails without this patch and passes
afterwards.
Because ADCX/ADOX need not be invoked through the VEX prefix, this
regression bisects to commit 16fc5726a6 ("target/i386: reimplement
0x0f 0x38, add AVX", 2022-10-18). However, the mistake happened a
little earlier, when BMI instructions were rewritten using the new
decoder framework.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1471
Reported-by: Paul Jolly <https://gitlab.com/myitcv>
Fixes: 1d0b926150 ("target/i386: move scalar 0F 38 and 0F 3A instruction to new decoder", 2022-10-18)
Cc: qemu-stable@nongnu.org
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
76 lines
2.1 KiB
C
76 lines
2.1 KiB
C
/* See if various BMI2 instructions give expected results */
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#define CC_C 1
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#define CC_O (1 << 11)
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#ifdef __x86_64__
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#define REG uint64_t
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#else
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#define REG uint32_t
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#endif
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void test_adox_adcx(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand)
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{
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REG flags;
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REG out_adcx, out_adox;
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asm("pushf; pop %0" : "=r"(flags));
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flags &= ~(CC_C | CC_O);
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flags |= (in_c ? CC_C : 0);
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flags |= (in_o ? CC_O : 0);
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out_adcx = adcx_operand;
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out_adox = adox_operand;
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asm("push %0; popf;"
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"adox %3, %2;"
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"adcx %3, %1;"
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"pushf; pop %0"
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: "+r" (flags), "+r" (out_adcx), "+r" (out_adox)
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: "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
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assert(out_adcx == in_c + adcx_operand - 1);
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assert(out_adox == in_o + adox_operand - 1);
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assert(!!(flags & CC_C) == (in_c || adcx_operand));
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assert(!!(flags & CC_O) == (in_o || adox_operand));
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}
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void test_adcx_adox(uint32_t in_c, uint32_t in_o, REG adcx_operand, REG adox_operand)
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{
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REG flags;
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REG out_adcx, out_adox;
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asm("pushf; pop %0" : "=r"(flags));
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flags &= ~(CC_C | CC_O);
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flags |= (in_c ? CC_C : 0);
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flags |= (in_o ? CC_O : 0);
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out_adcx = adcx_operand;
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out_adox = adox_operand;
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asm("push %0; popf;"
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"adcx %3, %1;"
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"adox %3, %2;"
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"pushf; pop %0"
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: "+r" (flags), "+r" (out_adcx), "+r" (out_adox)
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: "r" ((REG)-1), "0" (flags), "1" (out_adcx), "2" (out_adox));
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assert(out_adcx == in_c + adcx_operand - 1);
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assert(out_adox == in_o + adox_operand - 1);
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assert(!!(flags & CC_C) == (in_c || adcx_operand));
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assert(!!(flags & CC_O) == (in_o || adox_operand));
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}
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int main(int argc, char *argv[]) {
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/* try all combinations of input CF, input OF, CF from op1+op2, OF from op2+op1 */
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int i;
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for (i = 0; i <= 15; i++) {
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printf("%d\n", i);
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test_adcx_adox(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8));
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test_adox_adcx(!!(i & 1), !!(i & 2), !!(i & 4), !!(i & 8));
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}
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return 0;
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}
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