qemu/target-mips/mips-defs.h
ths b48cfdffd9 Throw RI for invalid MFMC0-class instructions. Introduce optional
MIPS_STRICT_STANDARD define to adhere more to the spec than it makes
sense in normal operation.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2650 c046a42c-6fe2-441c-8c8c-71466251a162
2007-04-11 02:24:14 +00:00

28 lines
712 B
C

#if !defined (__QEMU_MIPS_DEFS_H__)
#define __QEMU_MIPS_DEFS_H__
/* If we want to use 64 bits host regs... */
//#define USE_64BITS_REGS
/* If we want to use host float regs... */
//#define USE_HOST_FLOAT_REGS
/* real pages are variable size... */
#define TARGET_PAGE_BITS 12
/* Uses MIPS R4Kc TLB model */
#define MIPS_USES_R4K_TLB
#define MIPS_TLB_NB 16
#define MIPS_TLB_MAX 128
#ifdef TARGET_MIPS64
#define TARGET_LONG_BITS 64
#else
#define TARGET_LONG_BITS 32
#endif
/* Strictly follow the architecture standard: Disallow "special"
instruction handling for PMON/SPIM, force cycle-dependent
Count/Compare maintenance. */
//#define MIPS_STRICT_STANDARD 1
#endif /* !defined (__QEMU_MIPS_DEFS_H__) */