bdb97596f6
The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state history (SSH) and special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230707071213.9924-1-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
188 lines
6 KiB
C
188 lines
6 KiB
C
/*
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* QEMU PowerPC PowerNV XSCOM bus definitions
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_XSCOM_H
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#define PPC_PNV_XSCOM_H
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#include "exec/memory.h"
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#include "hw/ppc/pnv.h"
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typedef struct PnvXScomInterface PnvXScomInterface;
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#define TYPE_PNV_XSCOM_INTERFACE "pnv-xscom-interface"
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#define PNV_XSCOM_INTERFACE(obj) \
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INTERFACE_CHECK(PnvXScomInterface, (obj), TYPE_PNV_XSCOM_INTERFACE)
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typedef struct PnvXScomInterfaceClass PnvXScomInterfaceClass;
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DECLARE_CLASS_CHECKERS(PnvXScomInterfaceClass, PNV_XSCOM_INTERFACE,
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TYPE_PNV_XSCOM_INTERFACE)
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struct PnvXScomInterfaceClass {
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InterfaceClass parent;
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int (*dt_xscom)(PnvXScomInterface *dev, void *fdt, int offset);
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};
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/*
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* Layout of the XSCOM PCB addresses of EX core 1 (POWER 8)
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*
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* GPIO 0x1100xxxx
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* SCOM 0x1101xxxx
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* OHA 0x1102xxxx
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* CLOCK CTL 0x1103xxxx
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* FIR 0x1104xxxx
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* THERM 0x1105xxxx
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* <reserved> 0x1106xxxx
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* ..
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* 0x110Exxxx
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* PCB SLAVE 0x110Fxxxx
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*/
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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#define PNV_XSCOM_PSIHB_BASE 0x2010900
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#define PNV_XSCOM_PSIHB_SIZE 0x20
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV_XSCOM_PBA_BASE 0x2013f00
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#define PNV_XSCOM_PBA_SIZE 0x40
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#define PNV_XSCOM_PBCQ_NEST_BASE 0x2012000
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#define PNV_XSCOM_PBCQ_NEST_SIZE 0x46
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#define PNV_XSCOM_PBCQ_PCI_BASE 0x9012000
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#define PNV_XSCOM_PBCQ_PCI_SIZE 0x15
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#define PNV_XSCOM_PBCQ_SPCI_BASE 0x9013c00
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#define PNV_XSCOM_PBCQ_SPCI_SIZE 0x5
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/*
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* Layout of the XSCOM PCB addresses (POWER 9)
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*/
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#define PNV9_XSCOM_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV9_XSCOM_EC_SIZE 0x100000
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#define PNV9_XSCOM_EQ_BASE(core) \
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((uint64_t)(((core) & 0x1C) + 0x40) << 22)
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#define PNV9_XSCOM_EQ_SIZE 0x100000
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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#define PNV9_XSCOM_SBE_CTRL_BASE 0x00050008
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#define PNV9_XSCOM_SBE_CTRL_SIZE 0x1
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#define PNV9_XSCOM_SBE_MBOX_BASE 0x000D0050
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#define PNV9_XSCOM_SBE_MBOX_SIZE 0x16
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#define PNV9_XSCOM_PBA_BASE 0x5012b00
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#define PNV9_XSCOM_PBA_SIZE 0x40
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#define PNV9_XSCOM_PSIHB_BASE 0x5012900
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#define PNV9_XSCOM_PSIHB_SIZE 0x100
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#define PNV9_XSCOM_XIVE_BASE 0x5013000
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#define PNV9_XSCOM_XIVE_SIZE 0x300
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#define PNV9_XSCOM_PEC_NEST_BASE 0x4010c00
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#define PNV9_XSCOM_PEC_NEST_SIZE 0x100
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#define PNV9_XSCOM_PEC_PCI_BASE 0xd010800
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#define PNV9_XSCOM_PEC_PCI_SIZE 0x200
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/* XSCOM PCI "pass-through" window to PHB SCOM */
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#define PNV9_XSCOM_PEC_PCI_STK0 0x100
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#define PNV9_XSCOM_PEC_PCI_STK1 0x140
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#define PNV9_XSCOM_PEC_PCI_STK2 0x180
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/*
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* Layout of the XSCOM PCB addresses (POWER 10)
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*/
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#define PNV10_XSCOM_EQ_CHIPLET(core) (0x20 + ((core) >> 2))
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#define PNV10_XSCOM_EQ(chiplet) ((chiplet) << 24)
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#define PNV10_XSCOM_EC(proc) \
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((0x2 << 16) | ((1 << (3 - (proc))) << 12))
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#define PNV10_XSCOM_QME(chiplet) \
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(PNV10_XSCOM_EQ(chiplet) | (0xE << 16))
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/*
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* Make the region larger by 0x1000 (instead of starting at an offset) so the
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* modelled addresses start from 0
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*/
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#define PNV10_XSCOM_QME_BASE(core) \
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((uint64_t) PNV10_XSCOM_QME(PNV10_XSCOM_EQ_CHIPLET(core)))
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#define PNV10_XSCOM_QME_SIZE (0x8000 + 0x1000)
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#define PNV10_XSCOM_EQ_BASE(core) \
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((uint64_t) PNV10_XSCOM_EQ(PNV10_XSCOM_EQ_CHIPLET(core)))
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#define PNV10_XSCOM_EQ_SIZE 0x20000
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#define PNV10_XSCOM_EC_BASE(core) \
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((uint64_t) PNV10_XSCOM_EQ_BASE(core) | PNV10_XSCOM_EC(core & 0x3))
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#define PNV10_XSCOM_EC_SIZE 0x1000
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#define PNV10_XSCOM_PSIHB_BASE 0x3011D00
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#define PNV10_XSCOM_PSIHB_SIZE 0x100
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#define PNV10_XSCOM_OCC_BASE PNV9_XSCOM_OCC_BASE
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#define PNV10_XSCOM_OCC_SIZE PNV9_XSCOM_OCC_SIZE
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#define PNV10_XSCOM_SBE_CTRL_BASE PNV9_XSCOM_SBE_CTRL_BASE
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#define PNV10_XSCOM_SBE_CTRL_SIZE PNV9_XSCOM_SBE_CTRL_SIZE
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#define PNV10_XSCOM_SBE_MBOX_BASE PNV9_XSCOM_SBE_MBOX_BASE
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#define PNV10_XSCOM_SBE_MBOX_SIZE PNV9_XSCOM_SBE_MBOX_SIZE
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#define PNV10_XSCOM_PBA_BASE 0x01010CDA
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#define PNV10_XSCOM_PBA_SIZE 0x40
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#define PNV10_XSCOM_XIVE2_BASE 0x2010800
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#define PNV10_XSCOM_XIVE2_SIZE 0x400
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#define PNV10_XSCOM_PEC_NEST_BASE 0x3011800 /* index goes downwards ... */
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#define PNV10_XSCOM_PEC_NEST_SIZE 0x100
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#define PNV10_XSCOM_PEC_PCI_BASE 0x8010800 /* index goes upwards ... */
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#define PNV10_XSCOM_PEC_PCI_SIZE 0x200
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void pnv_xscom_realize(PnvChip *chip, uint64_t size, Error **errp);
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int pnv_dt_xscom(PnvChip *chip, void *fdt, int root_offset,
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uint64_t xscom_base, uint64_t xscom_size,
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const char *compat, int compat_size);
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void pnv_xscom_add_subregion(PnvChip *chip, hwaddr offset,
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MemoryRegion *mr);
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void pnv_xscom_region_init(MemoryRegion *mr,
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Object *owner,
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const MemoryRegionOps *ops,
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void *opaque,
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const char *name,
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uint64_t size);
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#endif /* PPC_PNV_XSCOM_H */
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