Joel Sing c13b169f1a RISC-V: Clear load reservations on context switch and SC ... This prevents a load reservation from being placed in one context/process, then being used in another, resulting in an SC succeeding incorrectly and breaking atomics. Signed-off-by: Joel Sing <joel@sing.id.au> Reviewed-by: Palmer Dabbelt <palmer@sifive.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-06-25 22:37:04 -07:00
..
insn_trans	RISC-V: Clear load reservations on context switch and SC	2019-06-25 22:37:04 -07:00
cpu-param.h
cpu.c	RISC-V: Clear load reservations on context switch and SC	2019-06-25 22:37:04 -07:00
cpu.h	RISC-V: Add support for the Zicsr extension	2019-06-25 22:32:42 -07:00
cpu_bits.h	target/riscv: Add the mcountinhibit CSR	2019-06-25 03:05:40 -07:00
cpu_helper.c	RISC-V: Clear load reservations on context switch and SC	2019-06-25 22:37:04 -07:00
cpu_user.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
csr.c	RISC-V: Add support for the Zicsr extension	2019-06-25 22:32:42 -07:00
fpu_helper.c
gdbstub.c	Include qemu-common.h exactly where needed	2019-06-12 13:20:20 +02:00
helper.h
insn16-32.decode
insn16-64.decode
insn16.decode
insn32-64.decode
insn32.decode
instmap.h	Supply missing header guards	2019-06-12 13:20:21 +02:00
Makefile.objs
op_helper.c	target/riscv: Use env_cpu, env_archcpu	2019-06-10 07:03:42 -07:00
pmp.c	RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off	2019-06-23 23:44:42 -07:00
pmp.h	RISC-V: Check for the effective memory privilege mode during PMP checks	2019-06-23 23:44:41 -07:00
trace-events
translate.c	RISC-V: Add support for the Zifencei extension	2019-06-25 22:31:21 -07:00