edf5ca5dbe
PCIDeviceClass and PCIDevice are defined in pci.h. Many users of the header don't actually need them. Similar structs live in their own headers: PCIBusClass and PCIBus in pci_bus.h, PCIBridge in pci_bridge.h, PCIHostBridgeClass and PCIHostState in pci_host.h, PCIExpressHost in pcie_host.h, and PCIERootPortClass, PCIEPort, and PCIESlot in pcie_port.h. Move PCIDeviceClass and PCIDeviceClass to new pci_device.h, along with the code that needs them. Adjust include directives. This also enables the next commit. Signed-off-by: Markus Armbruster <armbru@redhat.com> Message-Id: <20221222100330.380143-6-armbru@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
71 lines
1.9 KiB
C
71 lines
1.9 KiB
C
/*
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* QEMU PIIX South Bridge Emulation
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*
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* Copyright (c) 2006 Fabrice Bellard
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* Copyright (c) 2018 Hervé Poussineau
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#ifndef HW_SOUTHBRIDGE_PIIX_H
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#define HW_SOUTHBRIDGE_PIIX_H
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#include "hw/pci/pci_device.h"
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/* PIRQRC[A:D]: PIRQx Route Control Registers */
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#define PIIX_PIRQCA 0x60
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#define PIIX_PIRQCB 0x61
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#define PIIX_PIRQCC 0x62
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#define PIIX_PIRQCD 0x63
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/*
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* Reset Control Register: PCI-accessible ISA-Compatible Register at address
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* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
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*/
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#define PIIX_RCR_IOPORT 0xcf9
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#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
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#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
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struct PIIXState {
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PCIDevice dev;
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/*
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* bitmap to track pic levels.
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* The pic level is the logical OR of all the PCI irqs mapped to it
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* So one PIC level is tracked by PIIX_NUM_PIRQS bits.
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*
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* PIRQ is mapped to PIC pins, we track it by
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* PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
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* pic_irq * PIIX_NUM_PIRQS + pirq
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*/
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#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
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#error "unable to encode pic state in 64bit in pic_levels."
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#endif
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uint64_t pic_levels;
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qemu_irq *pic;
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/* This member isn't used. Just for save/load compatibility */
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int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
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/* Reset Control Register contents */
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uint8_t rcr;
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/* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
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MemoryRegion rcr_mem;
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};
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typedef struct PIIXState PIIX3State;
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#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
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DECLARE_INSTANCE_CHECKER(PIIX3State, PIIX3_PCI_DEVICE,
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TYPE_PIIX3_PCI_DEVICE)
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#define TYPE_PIIX3_DEVICE "PIIX3"
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#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
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#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
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#endif
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