Peter Maydell 68245e442c target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR ... Implement the MVE vector logical operations operating on two registers. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20210617121628.20116-12-peter.maydell@linaro.org		2021-06-21 17:12:50 +01:00
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alpha
arm	target/arm: Implement MVE VAND, VBIC, VORR, VORN, VEOR	2021-06-21 17:12:50 +01:00
avr
cris
hexagon
hppa	target/hppa: Remove unused 'memory.h' header	2021-06-05 21:23:14 +02:00
i386	x86 queue, 2021-06-18	2021-06-21 11:26:04 +01:00
m68k
microblaze
mips	target/mips: Fix 'Uncoditional' typo	2021-06-05 21:28:54 +02:00
nios2	target/nios2: fix page-fit instruction count	2021-06-05 21:17:10 +02:00
openrisc
ppc
riscv	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
rx
s390x
sh4
sparc
tricore
xtensa
meson.build