qemu/target
Michael Clark 71877e2969
RISC-V: Implement atomic mip/sip CSR updates
Use the new CSR read/modify/write interface to implement
atomic updates to mip/sip.

Signed-off-by: Michael Clark <mjc@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2019-01-09 10:00:52 -08:00
..
alpha target/alpha: Fix user-only initialization of fpcr 2019-01-08 09:04:30 +10:00
arm target-arm queue: 2019-01-07 16:56:33 +00:00
cris
hppa
i386 qdev-props: remove errp from GlobalProperty 2019-01-07 16:18:42 +04:00
lm32
m68k
microblaze
mips target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions 2019-01-03 17:52:52 +01:00
moxie
nios2
openrisc
ppc
riscv RISC-V: Implement atomic mip/sip CSR updates 2019-01-09 10:00:52 -08:00
s390x
sh4
sparc qdev-props: remove errp from GlobalProperty 2019-01-07 16:18:42 +04:00
tilegx
tricore
unicore32
xtensa