qemu/hw/isa/smc37c669-superio.c
Philippe Mathieu-Daudé 75cacb128b hw/isa/smc37c669: Change the parallel I/O base to 378H
On the Alpha DP264 machine, the Cirrus VGA is I/O mapped
in the 3C0H-3CFH range, thus I/O base used by the parallel
device clashes, and since a4cb773928 the VGA is not
working:

(qemu) info mtree
address-space: memory
  0000000000000000-ffffffffffffffff (prio 0, i/o): system
    00000801fc000000-00000801fdffffff (prio 0, i/o): pci0-io
      ...
      00000801fc0003b4-00000801fc0003b5 (prio 0, i/o): vga
      00000801fc0003ba-00000801fc0003ba (prio 0, i/o): vga
      00000801fc0003bc-00000801fc0003c3 (prio 0, i/o): parallel
                                    ^^^                ^^^^^^^^
      00000801fc0003c0-00000801fc0003cf (prio 0, i/o): vga
                   ^^^
      00000801fc0003d4-00000801fc0003d5 (prio 0, i/o): vga
      00000801fc0003da-00000801fc0003da (prio 0, i/o): vga
      ...

As there is no particular reason to use this base address
(introduced in 7bea0dd434), change to 378H which is the
default on PC machines.

Reported-by: Emilio G. Cota <cota@braap.org>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Tested-by: Emilio G. Cota <cota@braap.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20180614233935.26585-1-f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2018-06-16 19:46:54 -10:00

116 lines
2.6 KiB
C

/*
* SMC FDC37C669 Super I/O controller
*
* Copyright (c) 2018 Philippe Mathieu-Daudé
*
* This code is licensed under the GNU GPLv2 and later.
* See the COPYING file in the top-level directory.
* SPDX-License-Identifier: GPL-2.0-or-later
*/
#include "qemu/osdep.h"
#include "hw/isa/superio.h"
/* UARTs (compatible with NS16450 or PC16550) */
static bool is_serial_enabled(ISASuperIODevice *sio, uint8_t index)
{
return index < 2;
}
static uint16_t get_serial_iobase(ISASuperIODevice *sio, uint8_t index)
{
return index ? 0x2f8 : 0x3f8;
}
static unsigned int get_serial_irq(ISASuperIODevice *sio, uint8_t index)
{
return index ? 3 : 4;
}
/* Parallel port */
static bool is_parallel_enabled(ISASuperIODevice *sio, uint8_t index)
{
return index < 1;
}
static uint16_t get_parallel_iobase(ISASuperIODevice *sio, uint8_t index)
{
return 0x378;
}
static unsigned int get_parallel_irq(ISASuperIODevice *sio, uint8_t index)
{
return 7;
}
static unsigned int get_parallel_dma(ISASuperIODevice *sio, uint8_t index)
{
return 3;
}
/* Diskette controller (Software compatible with the Intel PC8477) */
static bool is_fdc_enabled(ISASuperIODevice *sio, uint8_t index)
{
return index < 1;
}
static uint16_t get_fdc_iobase(ISASuperIODevice *sio, uint8_t index)
{
return 0x3f0;
}
static unsigned int get_fdc_irq(ISASuperIODevice *sio, uint8_t index)
{
return 6;
}
static unsigned int get_fdc_dma(ISASuperIODevice *sio, uint8_t index)
{
return 2;
}
static void smc37c669_class_init(ObjectClass *klass, void *data)
{
ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass);
sc->parallel = (ISASuperIOFuncs){
.count = 1,
.is_enabled = is_parallel_enabled,
.get_iobase = get_parallel_iobase,
.get_irq = get_parallel_irq,
.get_dma = get_parallel_dma,
};
sc->serial = (ISASuperIOFuncs){
.count = 2,
.is_enabled = is_serial_enabled,
.get_iobase = get_serial_iobase,
.get_irq = get_serial_irq,
};
sc->floppy = (ISASuperIOFuncs){
.count = 1,
.is_enabled = is_fdc_enabled,
.get_iobase = get_fdc_iobase,
.get_irq = get_fdc_irq,
.get_dma = get_fdc_dma,
};
sc->ide.count = 0;
}
static const TypeInfo smc37c669_type_info = {
.name = TYPE_SMC37C669_SUPERIO,
.parent = TYPE_ISA_SUPERIO,
.instance_size = sizeof(ISASuperIODevice),
.class_size = sizeof(ISASuperIOClass),
.class_init = smc37c669_class_init,
};
static void smc37c669_register_types(void)
{
type_register_static(&smc37c669_type_info);
}
type_init(smc37c669_register_types)