0f936247e8
The PCI_COMMAND register is located at offset 4 within
the PCI configuration space and occupies 2 bytes. The
interrupt disable bit is at the 10th bit, which corresponds
to the byte at offset 5 in the PCI configuration space.
In our testing environment, the guest driver may directly
updates the byte at offset 5 in the PCI configuration space.
The backtrace looks like as following:
at hw/pci/pci.c:1442
at hw/virtio/virtio-pci.c:605
val=5, len=1) at hw/pci/pci_host.c:81
In this situation, the range_covers_byte function called
by the pci_default_write_config function will return false,
resulting in the inability to handle the interrupt disable
update event.
To fix this issue, we can use the ranges_overlap function
instead of range_covers_byte to determine whether the interrupt
bit has been updated.
Signed-off-by: Guoyi Tu <tugy@chinatelecom.cn>
Signed-off-by: yuanminghao <yuanmh12@chinatelecom.cn>
Message-Id: <ce2d0437-8faa-4d61-b536-4668f645a959@chinatelecom.cn>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Fixes:
|
||
|---|---|---|
| .. | ||
| Kconfig | ||
| meson.build | ||
| msi.c | ||
| msix.c | ||
| pci-hmp-cmds.c | ||
| pci-internal.h | ||
| pci-qmp-cmds.c | ||
| pci-stub.c | ||
| pci.c | ||
| pci_bridge.c | ||
| pci_host.c | ||
| pcie.c | ||
| pcie_aer.c | ||
| pcie_doe.c | ||
| pcie_host.c | ||
| pcie_port.c | ||
| pcie_sriov.c | ||
| shpc.c | ||
| slotid_cap.c | ||
| trace-events | ||
| trace.h | ||