qemu/target/ppc/translate
Nicholas Piggin f64f1f8704 target/ppc: Fix LQ, STQ register-pair order for big-endian
LQ, STQ have the same register-pair ordering as LQARX/STQARX., which is
the even (lower) register contains the most significant bits. This is
not implemented correctly for big-endian.

do_ldst_quad() has variables low_addr_gpr and high_addr_gpr which is
confusing because they are low and high addresses, whereas LQARX/STQARX.
and most such things use the low and high values for lo/hi variables.
The conversion to native 128-bit memory access functions missed this
strangeness.

Fix this by changing the if condition, and change the variable names to
hi/lo to match convention.

Cc: qemu-stable@nongnu.org
Reported-by: Ivan Warren <ivan@vmfacility.fr>
Fixes: 57b38ffd0c ("target/ppc: Use tcg_gen_qemu_{ld,st}_i128 for LQARX, LQ, STQ")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1836
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
(cherry picked from commit 718209358f2e4f231cbacf974c3299c4fe7beb83)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2023-09-21 19:35:19 +03:00
..
branch-impl.c.inc target/ppc: Inline gen_icount_io_start() 2023-06-05 12:04:29 -07:00
dfp-impl.c.inc
fixedpoint-impl.c.inc target/ppc: Fix LQ, STQ register-pair order for big-endian 2023-09-21 19:35:19 +03:00
fp-impl.c.inc target/ppc: Fix fallback to MFSS for MFFS* instructions on pre 3.0 ISAs 2023-05-27 08:25:19 -03:00
fp-ops.c.inc
processor-ctrl-impl.c.inc
spe-impl.c.inc
spe-ops.c.inc
storage-ctrl-impl.c.inc
vmx-impl.c.inc
vmx-ops.c.inc
vsx-impl.c.inc
vsx-ops.c.inc