Frank Chang d2c1a177b1 target/riscv: rvb: add b-ext version cpu option ... Default b-ext version is v0.93. Signed-off-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210505160620.15723-18-frank.chang@sifive.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-06-08 09:59:46 +10:00
..
insn_trans	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
arch_dump.c
bitmanip_helper.c	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
cpu-param.h
cpu.c	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
cpu.h	target/riscv: rvb: add b-ext version cpu option	2021-06-08 09:59:46 +10:00
cpu_bits.h	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
cpu_helper.c
cpu_user.h
csr.c
fpu_helper.c
gdbstub.c
helper.h	target/riscv: rvb: generalized or-combine	2021-06-08 09:59:45 +10:00
insn16.decode	target/riscv: Consolidate RV32/64 16-bit instructions	2021-05-11 20:02:07 +10:00
insn32.decode	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
instmap.h
internals.h
machine.c
meson.build	target/riscv: rvb: generalized reverse	2021-06-08 09:59:45 +10:00
monitor.c
op_helper.c	target/riscv: fix wfi exception behavior	2021-06-08 09:59:42 +10:00
pmp.c	target/riscv/pmp: Add assert for ePMP operations	2021-06-08 09:59:43 +10:00
pmp.h
trace-events
trace.h
translate.c	target/riscv: rvb: add/shift with prefix zero-extend	2021-06-08 09:59:45 +10:00
vector_helper.c