Richard Henderson c2ffd7549b accel/tcg: Record singlestep_enabled in tb->cflags ... Set CF_SINGLE_STEP when single-stepping is enabled. This avoids the need to flush all tb's when turning single-stepping on or off. Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>		2021-07-21 07:47:05 -10:00
..
user
address-spaces.h
confidential-guest-support.h
cpu-all.h
cpu-common.h	memory: Introduce RAM_NORESERVE and wire it up in qemu_ram_mmap()	2021-06-15 20:27:38 +02:00
cpu-defs.h
cpu_ldst.h
cputlb.h
exec-all.h	accel/tcg: Record singlestep_enabled in tb->cflags	2021-07-21 07:47:05 -10:00
gdbstub.h
gen-icount.h
helper-gen.h
helper-head.h	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
helper-proto.h
helper-tcg.h	tcg: Combine dh_is_64bit and dh_is_signed to dh_typecode	2021-06-19 08:51:11 -07:00
hwaddr.h
ioport.h
log.h
memattrs.h
memop.h
memory-internal.h
memory.h	softmmu/physmem: Extend ram_block_discard_(require|disable) by two discard types	2021-07-08 15:54:45 -04:00
memory_ldst.h.inc	exec/memory_ldst: Use correct type sizes	2021-05-26 08:35:51 -07:00
memory_ldst_cached.h.inc	exec/memory_ldst_cached: Use correct type size	2021-05-26 08:35:51 -07:00
memory_ldst_phys.h.inc	exec/memory_ldst_phys: Use correct type sizes	2021-05-26 08:35:51 -07:00
page-vary.h
plugin-gen.h
poison.h
ram_addr.h	memory: Introduce RAM_NORESERVE and wire it up in qemu_ram_mmap()	2021-06-15 20:27:38 +02:00
ramblock.h
ramlist.h
softmmu-semi.h
target_page.h
translate-all.h
translator.h	accel/tcg: Remove TranslatorOps.breakpoint_check	2021-07-21 07:47:05 -10:00