e844f0c5d0
OBJECT_DECLARE_SIMPLE_TYPE() macro provides the OrIRQState declaration for free. Besides, the QOM code style is to use the structure name as typedef, and QEMU style is to use Camel Case, so rename qemu_or_irq as OrIRQState. Mechanical change using: $ sed -i -e 's/qemu_or_irq/OrIRQState/g' $(git grep -l qemu_or_irq) Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20230113200138.52869-5-philmd@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
130 lines
4.5 KiB
C
130 lines
4.5 KiB
C
/*
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* Samsung exynos4210 SoC emulation
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*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved.
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* Maksim Kozlov <m.kozlov@samsung.com>
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* Evgeny Voevodin <e.voevodin@samsung.com>
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* Igor Mitsyanko <i.mitsyanko@samsung.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef EXYNOS4210_H
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#define EXYNOS4210_H
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#include "hw/or-irq.h"
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#include "hw/sysbus.h"
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#include "hw/cpu/a9mpcore.h"
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#include "hw/intc/exynos4210_gic.h"
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#include "hw/intc/exynos4210_combiner.h"
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#include "hw/core/split-irq.h"
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#include "target/arm/cpu-qom.h"
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#include "qom/object.h"
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#define EXYNOS4210_NCPUS 2
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#define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000
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#define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000
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#define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */
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#define EXYNOS4210_IROM_BASE_ADDR 0x00000000
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#define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000
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#define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */
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#define EXYNOS4210_IRAM_BASE_ADDR 0x02020000
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#define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */
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/* Secondary CPU startup code is in IROM memory */
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#define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR
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#define EXYNOS4210_SMP_BOOT_SIZE 0x1000
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#define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR
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/* Secondary CPU polling address to get loader start from */
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#define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814
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#define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000
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#define EXYNOS4210_L2X0_BASE_ADDR 0x10502000
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/*
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* exynos4210 IRQ subsystem stub definitions.
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*/
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#define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */
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#define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64
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#define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16
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#define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \
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(EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8)
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#define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \
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(EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8)
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#define EXYNOS4210_I2C_NUMBER 9
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#define EXYNOS4210_NUM_DMA 3
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/*
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* We need one splitter for every external combiner input, plus
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* one for every non-zero entry in combiner_grp_to_gic_id[],
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* minus one for every external combiner ID in second or later
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* places in a combinermap[] line.
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* We'll assert in exynos4210_init_board_irqs() if this is wrong.
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*/
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#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38)
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struct Exynos4210State {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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ARMCPU *cpu[EXYNOS4210_NCPUS];
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qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ];
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MemoryRegion chipid_mem;
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MemoryRegion iram_mem;
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MemoryRegion irom_mem;
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MemoryRegion irom_alias_mem;
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MemoryRegion boot_secondary;
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MemoryRegion bootreg_mem;
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I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
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OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA];
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OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS];
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A9MPPrivState a9mpcore;
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Exynos4210GicState ext_gic;
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Exynos4210CombinerState int_combiner;
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Exynos4210CombinerState ext_combiner;
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SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS];
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};
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#define TYPE_EXYNOS4210_SOC "exynos4210"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC)
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void exynos4210_write_secondary(ARMCPU *cpu,
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const struct arm_boot_info *info);
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/* Get IRQ number from exynos4210 IRQ subsystem stub.
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* To identify IRQ source use internal combiner group and bit number
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* grp - group number
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* bit - bit number inside group */
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uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit);
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/*
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* exynos4210 UART
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*/
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DeviceState *exynos4210_uart_create(hwaddr addr,
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int fifo_size,
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int channel,
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Chardev *chr,
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qemu_irq irq);
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#endif /* EXYNOS4210_H */
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