bdb97596f6
The Quad Management Engine (QME) manages power related settings for its quad. The xscom region is separate from the quad xscoms, therefore a new region is added. The xscoms in a QME select a given core by selecting the forth nibble. Implement dummy reads for the stop state history (SSH) and special wakeup (SPWU) registers. This quietens some sxcom errors when skiboot boots on p10. Power9 does not have a QME. Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-ID: <20230707071213.9924-1-joel@jms.id.au> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
89 lines
2.1 KiB
C
89 lines
2.1 KiB
C
/*
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* QEMU PowerPC PowerNV CPU Core model
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*
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* Copyright (c) 2016, IBM Corporation.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public License
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* as published by the Free Software Foundation; either version 2.1 of
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* the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef PPC_PNV_CORE_H
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#define PPC_PNV_CORE_H
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#include "hw/cpu/core.h"
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#include "target/ppc/cpu.h"
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#include "hw/ppc/pnv.h"
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#include "qom/object.h"
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#define TYPE_PNV_CORE "powernv-cpu-core"
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OBJECT_DECLARE_TYPE(PnvCore, PnvCoreClass,
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PNV_CORE)
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struct PnvCore {
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/*< private >*/
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CPUCore parent_obj;
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/*< public >*/
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PowerPCCPU **threads;
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uint32_t pir;
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uint64_t hrmor;
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PnvChip *chip;
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MemoryRegion xscom_regs;
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};
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struct PnvCoreClass {
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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uint64_t xscom_size;
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};
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#define PNV_CORE_TYPE_SUFFIX "-" TYPE_PNV_CORE
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#define PNV_CORE_TYPE_NAME(cpu_model) cpu_model PNV_CORE_TYPE_SUFFIX
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typedef struct PnvCPUState {
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Object *intc;
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} PnvCPUState;
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static inline PnvCPUState *pnv_cpu_state(PowerPCCPU *cpu)
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{
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return (PnvCPUState *)cpu->machine_data;
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}
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struct PnvQuadClass {
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DeviceClass parent_class;
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const MemoryRegionOps *xscom_ops;
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uint64_t xscom_size;
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const MemoryRegionOps *xscom_qme_ops;
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uint64_t xscom_qme_size;
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};
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#define TYPE_PNV_QUAD "powernv-cpu-quad"
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#define PNV_QUAD_TYPE_SUFFIX "-" TYPE_PNV_QUAD
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#define PNV_QUAD_TYPE_NAME(cpu_model) cpu_model PNV_QUAD_TYPE_SUFFIX
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OBJECT_DECLARE_TYPE(PnvQuad, PnvQuadClass, PNV_QUAD)
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struct PnvQuad {
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DeviceState parent_obj;
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uint32_t quad_id;
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MemoryRegion xscom_regs;
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MemoryRegion xscom_qme_regs;
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};
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#endif /* PPC_PNV_CORE_H */
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