qemu/target/hppa
Helge Deller f8c0fd9804 target/hppa: Move iaoq registers and thus reduce generated code size
On hppa the Instruction Address Offset Queue (IAOQ) registers specifies
the next to-be-executed instructions addresses. Each generated TB writes those
registers at least once, so those registers are used heavily in generated
code.

Looking at the generated assembly, for a x86-64 host this code
to write the address $0x7ffe826f into iaoq_f is generated:
0x7f73e8000184:  c7 85 d4 01 00 00 6f 82  movl     $0x7ffe826f, 0x1d4(%rbp)
0x7f73e800018c:  fe 7f
0x7f73e800018e:  c7 85 d8 01 00 00 73 82  movl     $0x7ffe8273, 0x1d8(%rbp)
0x7f73e8000196:  fe 7f

With the trivial change, by moving the variables iaoq_f and iaoq_b to
the top of struct CPUArchState, the offset to %rbp is reduced (from
0x1d4 to 0), which allows the x86-64 tcg to generate 3 bytes less of
generated code per move instruction:
0x7fc1e800018c:  c7 45 00 6f 82 fe 7f     movl     $0x7ffe826f, (%rbp)
0x7fc1e8000193:  c7 45 04 73 82 fe 7f     movl     $0x7ffe8273, 4(%rbp)

Overall this is a reduction of generated code (not a reduction of
number of instructions).
A test run with checks the generated code size by running "/bin/ls"
with qemu-user shows that the code size shrinks from 1616767 to 1569273
bytes, which is ~97% of the former size.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Helge Deller <deller@gmx.de>
Cc: qemu-stable@nongnu.org
2023-08-04 00:02:56 +02:00
..
cpu-param.h target/hppa: Remove NB_MMU_MODES define 2023-03-13 06:44:37 -07:00
cpu-qom.h target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro 2022-03-06 22:23:09 +01:00
cpu.c target/hppa: Replace tb_pc() with tb->pc 2023-03-01 07:33:21 -10:00
cpu.h target/hppa: Move iaoq registers and thus reduce generated code size 2023-08-04 00:02:56 +02:00
fpu_helper.c target/hppa: Extract FPU helpers to fpu_helper.c 2023-02-27 22:29:01 +01:00
gdbstub.c gdbstub: move register helpers into standalone include 2023-03-07 20:44:08 +00:00
helper.c linux-user/hppa: Dump IIR on register dump 2022-09-27 09:29:33 +02:00
helper.h tcg: Remove dh_alias indirection for dh_typecode 2022-02-28 08:04:06 -10:00
insns.decode target/hppa: Fix fid instruction emulation 2022-12-19 23:14:06 +01:00
int_helper.c other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
Kconfig meson: Introduce target-specific Kconfig 2021-07-09 18:21:34 +02:00
machine.c migration: Replace migration's JSON writer by the general one 2020-12-19 10:39:16 +01:00
mem_helper.c exec/exec-all: Move 'qemu/log.h' include in units requiring it 2022-02-21 10:18:06 +01:00
meson.build meson: Replace softmmu_ss -> system_ss 2023-06-20 10:01:30 +02:00
op_helper.c accel/tcg: Return bool from page_check_range 2023-07-15 08:02:32 +01:00
sys_helper.c target/hppa: Extract system helpers to sys_helper.c 2023-02-27 22:29:01 +01:00
trace-events docs: fix references to docs/devel/tracing.rst 2021-06-02 06:51:09 +02:00
trace.h trace: switch position of headers to what Meson requires 2020-08-21 06:18:24 -04:00
translate.c other architectures: spelling fixes 2023-07-25 17:14:07 +03:00