e975434d62
Otherwise tcg_handle_interrupt() triggers an assertion failure: #5 0x0000555555c97369 in tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:83 #6 tcg_handle_interrupt (cpu=0x555557434cb0, mask=2) at ../accel/tcg/tcg-accel-ops.c:81 #7 0x0000555555b4d58b in pic_irq_request (opaque=<optimized out>, irq=<optimized out>, level=1) at ../hw/i386/x86.c:555 #8 0x0000555555b4f218 in gsi_handler (opaque=0x5555579423d0, n=13, level=1) at ../hw/i386/x86.c:611 #9 0x00007fffa42bde14 in code_gen_buffer () #10 0x0000555555c724bb in cpu_tb_exec (cpu=cpu@entry=0x555557434cb0, itb=<optimized out>, tb_exit=tb_exit@entry=0x7fffe9bfd658) at ../accel/tcg/cpu-exec.c:457 Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1808 Reported-by: NyanCatTW1 <https://gitlab.com/a0939712328> Co-developed-by: Richard Henderson <richard.henderson@linaro.org>' Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> (cherry picked from commit c1f27a0c6ae4059a1d809e9c2bc4d47b823c32a3) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
64 lines
1.9 KiB
C
64 lines
1.9 KiB
C
/*
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* x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers (sysemu code)
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/main-loop.h"
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#include "cpu.h"
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#include "hw/irq.h"
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static qemu_irq ferr_irq;
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void x86_register_ferr_irq(qemu_irq irq)
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{
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ferr_irq = irq;
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}
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void fpu_check_raise_ferr_irq(CPUX86State *env)
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{
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if (ferr_irq && !(env->hflags2 & HF2_IGNNE_MASK)) {
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qemu_mutex_lock_iothread();
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qemu_irq_raise(ferr_irq);
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qemu_mutex_unlock_iothread();
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return;
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}
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}
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void cpu_clear_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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env->hflags2 &= ~HF2_IGNNE_MASK;
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}
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void cpu_set_ignne(void)
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{
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CPUX86State *env = &X86_CPU(first_cpu)->env;
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assert(qemu_mutex_iothread_locked());
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env->hflags2 |= HF2_IGNNE_MASK;
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/*
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* We get here in response to a write to port F0h. The chipset should
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* deassert FP_IRQ and FERR# instead should stay signaled until FPSW_SE is
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* cleared, because FERR# and FP_IRQ are two separate pins on real
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* hardware. However, we don't model FERR# as a qemu_irq, so we just
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* do directly what the chipset would do, i.e. deassert FP_IRQ.
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*/
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qemu_irq_lower(ferr_irq);
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}
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