958e1dd130
Many instructions which load/store 128-bit values are supposed to raise #GP when the memory operand isn't 16-byte aligned. This includes: - Instructions explicitly requiring memory alignment (Exceptions Type 1 in the "AVX and SSE Instruction Exception Specification" section of the SDM) - Legacy SSE instructions that load/store 128-bit values (Exceptions Types 2 and 4). This change sets MO_ALIGN_16 on 128-bit memory accesses that require 16-byte alignment. It adds cpu_record_sigbus and cpu_do_unaligned_access hooks that simulate a #GP exception in qemu-user and qemu-system, respectively. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/217 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Ricky Zhou <ricky@rzhou.org> Message-Id: <20220830034816.57091-2-ricky@rzhou.org> [Do not bother checking PREFIX_VEX, since AVX is not supported. - Paolo] Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
58 lines
2 KiB
C
58 lines
2 KiB
C
/*
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* x86 exception helpers - user-mode specific code
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "tcg/helper-tcg.h"
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void x86_cpu_record_sigsegv(CPUState *cs, vaddr addr,
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MMUAccessType access_type,
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bool maperr, uintptr_t ra)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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/*
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* The error_code that hw reports as part of the exception frame
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* is copied to linux sigcontext.err. The exception_index is
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* copied to linux sigcontext.trapno. Short of inventing a new
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* place to store the trapno, we cannot let our caller raise the
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* signal and set exception_index to EXCP_INTERRUPT.
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*/
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env->cr[2] = addr;
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env->error_code = ((access_type == MMU_DATA_STORE) << PG_ERROR_W_BIT)
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| (maperr ? 0 : PG_ERROR_P_MASK)
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| PG_ERROR_U_MASK;
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cs->exception_index = EXCP0E_PAGE;
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/* Disable do_interrupt_user. */
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env->exception_is_int = 0;
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env->exception_next_eip = -1;
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cpu_loop_exit_restore(cs, ra);
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}
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void x86_cpu_record_sigbus(CPUState *cs, vaddr addr,
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MMUAccessType access_type, uintptr_t ra)
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{
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X86CPU *cpu = X86_CPU(cs);
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handle_unaligned_access(&cpu->env, addr, access_type, ra);
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}
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