qemu/tests/libqos/pci-pc.c
David Gibson b8cc4d0231 libqos: Move BAR assignment to common code
The PCI backends in libqos each supply an iomap() and iounmap() function
which is used to set up a specified PCI BAR.  But PCI BAR allocation takes
place entirely within PCI space, so doesn't really need per-backend
versions.  For example, Linux includes generic BAR allocation code used on
platforms where that isn't done by firmware.

This patch merges the BAR allocation from the two existing backends into a
single simplified copy.  The back ends just need to set up some parameters
describing the window of PCI IO and PCI memory addresses which are
available for allocation.  Like both the existing versions the new one uses
a simple bump allocator.

Note that (again like the existing versions) this doesn't really handle
64-bit memory BARs properly.  It is actually used for such a BAR by the
ivshmem test, and apparently the 32-bit MMIO BAR logic is close enough to
work, as long as the BAR isn't too big.  Fixing that to properly handle
64-bit BAR allocation is a problem for another time.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
2016-10-28 09:38:27 +11:00

193 lines
4.5 KiB
C

/*
* libqos PCI bindings for PC
*
* Copyright IBM, Corp. 2012-2013
*
* Authors:
* Anthony Liguori <aliguori@us.ibm.com>
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
*/
#include "qemu/osdep.h"
#include "libqtest.h"
#include "libqos/pci-pc.h"
#include "hw/pci/pci_regs.h"
#include "qemu-common.h"
#define ACPI_PCIHP_ADDR 0xae00
#define PCI_EJ_BASE 0x0008
typedef struct QPCIBusPC
{
QPCIBus bus;
} QPCIBusPC;
static uint8_t qpci_pc_pio_readb(QPCIBus *bus, uint32_t addr)
{
return inb(addr);
}
static uint8_t qpci_pc_mmio_readb(QPCIBus *bus, uint32_t addr)
{
return readb(addr);
}
static void qpci_pc_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
{
outb(addr, val);
}
static void qpci_pc_mmio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
{
writeb(addr, val);
}
static uint16_t qpci_pc_pio_readw(QPCIBus *bus, uint32_t addr)
{
return inw(addr);
}
static uint16_t qpci_pc_mmio_readw(QPCIBus *bus, uint32_t addr)
{
return readw(addr);
}
static void qpci_pc_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
{
outw(addr, val);
}
static void qpci_pc_mmio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
{
writew(addr, val);
}
static uint32_t qpci_pc_pio_readl(QPCIBus *bus, uint32_t addr)
{
return inl(addr);
}
static uint32_t qpci_pc_mmio_readl(QPCIBus *bus, uint32_t addr)
{
return readl(addr);
}
static void qpci_pc_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
{
outl(addr, val);
}
static void qpci_pc_mmio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
{
writel(addr, val);
}
static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inb(0xcfc);
}
static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inw(0xcfc);
}
static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
return inl(0xcfc);
}
static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outb(0xcfc, value);
}
static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outw(0xcfc, value);
}
static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value)
{
outl(0xcf8, (1U << 31) | (devfn << 8) | offset);
outl(0xcfc, value);
}
QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
{
QPCIBusPC *ret;
ret = g_malloc(sizeof(*ret));
ret->bus.pio_readb = qpci_pc_pio_readb;
ret->bus.pio_readw = qpci_pc_pio_readw;
ret->bus.pio_readl = qpci_pc_pio_readl;
ret->bus.pio_writeb = qpci_pc_pio_writeb;
ret->bus.pio_writew = qpci_pc_pio_writew;
ret->bus.pio_writel = qpci_pc_pio_writel;
ret->bus.mmio_readb = qpci_pc_mmio_readb;
ret->bus.mmio_readw = qpci_pc_mmio_readw;
ret->bus.mmio_readl = qpci_pc_mmio_readl;
ret->bus.mmio_writeb = qpci_pc_mmio_writeb;
ret->bus.mmio_writew = qpci_pc_mmio_writew;
ret->bus.mmio_writel = qpci_pc_mmio_writel;
ret->bus.config_readb = qpci_pc_config_readb;
ret->bus.config_readw = qpci_pc_config_readw;
ret->bus.config_readl = qpci_pc_config_readl;
ret->bus.config_writeb = qpci_pc_config_writeb;
ret->bus.config_writew = qpci_pc_config_writew;
ret->bus.config_writel = qpci_pc_config_writel;
ret->bus.pio_alloc_ptr = 0xc000;
ret->bus.mmio_alloc_ptr = 0xE0000000;
ret->bus.mmio_limit = 0x100000000ULL;
return &ret->bus;
}
void qpci_free_pc(QPCIBus *bus)
{
QPCIBusPC *s = container_of(bus, QPCIBusPC, bus);
g_free(s);
}
void qpci_unplug_acpi_device_test(const char *id, uint8_t slot)
{
QDict *response;
char *cmd;
cmd = g_strdup_printf("{'execute': 'device_del',"
" 'arguments': {"
" 'id': '%s'"
"}}", id);
response = qmp(cmd);
g_free(cmd);
g_assert(response);
g_assert(!qdict_haskey(response, "error"));
QDECREF(response);
outb(ACPI_PCIHP_ADDR + PCI_EJ_BASE, 1 << slot);
response = qmp("");
g_assert(response);
g_assert(qdict_haskey(response, "event"));
g_assert(!strcmp(qdict_get_str(response, "event"), "DEVICE_DELETED"));
QDECREF(response);
}