4e5712f903
Pack the quotient and remainder into a single Int128. Use the divu128 primitive to remove the cpu_abort on 32-bit hosts. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- v2: Extended div test case to cover these insns.
76 lines
1.4 KiB
C
76 lines
1.4 KiB
C
#include <assert.h>
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#include <stdint.h>
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static void test_dr(void)
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{
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register int32_t r0 asm("r0") = -1;
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register int32_t r1 asm("r1") = -4241;
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int32_t b = 101, q, r;
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asm("dr %[r0],%[b]"
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: [r0] "+r" (r0), [r1] "+r" (r1)
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: [b] "r" (b)
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: "cc");
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q = r1;
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r = r0;
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assert(q == -41);
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assert(r == -100);
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}
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static void test_dlr(void)
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{
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register uint32_t r0 asm("r0") = 0;
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register uint32_t r1 asm("r1") = 4243;
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uint32_t b = 101, q, r;
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asm("dlr %[r0],%[b]"
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: [r0] "+r" (r0), [r1] "+r" (r1)
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: [b] "r" (b)
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: "cc");
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q = r1;
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r = r0;
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assert(q == 42);
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assert(r == 1);
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}
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static void test_dsgr(void)
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{
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register int64_t r0 asm("r0") = -1;
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register int64_t r1 asm("r1") = -4241;
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int64_t b = 101, q, r;
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asm("dsgr %[r0],%[b]"
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: [r0] "+r" (r0), [r1] "+r" (r1)
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: [b] "r" (b)
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: "cc");
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q = r1;
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r = r0;
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assert(q == -41);
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assert(r == -100);
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}
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static void test_dlgr(void)
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{
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register uint64_t r0 asm("r0") = 0;
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register uint64_t r1 asm("r1") = 4243;
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uint64_t b = 101, q, r;
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asm("dlgr %[r0],%[b]"
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: [r0] "+r" (r0), [r1] "+r" (r1)
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: [b] "r" (b)
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: "cc");
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q = r1;
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r = r0;
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assert(q == 42);
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assert(r == 1);
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}
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int main(void)
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{
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test_dr();
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test_dlr();
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test_dsgr();
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test_dlgr();
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return 0;
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}
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