6da4433fc5
The DRAM address of a DMA transaction depends on the DRAM base address of the SoC. Inform the SMC controller model with this value. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Message-id: 20190618165311.27066-15-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| aspeed_smc.h | ||
| imx_spi.h | ||
| mss-spi.h | ||
| pl022.h | ||
| ssi.h | ||
| stm32f2xx_spi.h | ||
| xilinx_spips.h | ||