54ee564132
In order to correctly report secure boot running firmware the values of certain registers must be set. We don't yet have documentation from ASPEED on what they mean. The meaning is inferred from u-boot's use of them. Introduce properties so the settings can be configured per-machine. Reviewed-by: Peter Delevoryas <pdel@fb.com> Tested-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20220628154740.1117349-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
46 lines
1.1 KiB
C
46 lines
1.1 KiB
C
/*
|
|
* ASPEED Secure Boot Controller
|
|
*
|
|
* Copyright (C) 2021-2022 IBM Corp.
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
|
*/
|
|
|
|
#ifndef ASPEED_SBC_H
|
|
#define ASPEED_SBC_H
|
|
|
|
#include "hw/sysbus.h"
|
|
|
|
#define TYPE_ASPEED_SBC "aspeed.sbc"
|
|
#define TYPE_ASPEED_AST2600_SBC TYPE_ASPEED_SBC "-ast2600"
|
|
OBJECT_DECLARE_TYPE(AspeedSBCState, AspeedSBCClass, ASPEED_SBC)
|
|
|
|
#define ASPEED_SBC_NR_REGS (0x93c >> 2)
|
|
|
|
#define QSR_AES BIT(27)
|
|
#define QSR_RSA1024 (0x0 << 12)
|
|
#define QSR_RSA2048 (0x1 << 12)
|
|
#define QSR_RSA3072 (0x2 << 12)
|
|
#define QSR_RSA4096 (0x3 << 12)
|
|
#define QSR_SHA224 (0x0 << 10)
|
|
#define QSR_SHA256 (0x1 << 10)
|
|
#define QSR_SHA384 (0x2 << 10)
|
|
#define QSR_SHA512 (0x3 << 10)
|
|
|
|
struct AspeedSBCState {
|
|
SysBusDevice parent;
|
|
|
|
bool emmc_abr;
|
|
uint32_t signing_settings;
|
|
|
|
MemoryRegion iomem;
|
|
|
|
uint32_t regs[ASPEED_SBC_NR_REGS];
|
|
};
|
|
|
|
struct AspeedSBCClass {
|
|
SysBusDeviceClass parent_class;
|
|
};
|
|
|
|
#endif /* ASPEED_SBC_H */
|