1b18d1fa05
Although we still can't use ldrd and strd for all operations, increase the chances by getting the register allocation correct. Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
28 lines
695 B
C
28 lines
695 B
C
/* SPDX-License-Identifier: MIT */
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/*
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* Define Arm target-specific operand constraints.
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* Copyright (c) 2021 Linaro
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*/
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/*
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* Define constraint letters for register sets:
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* REGS(letter, register_mask)
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*/
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REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
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REGS('r', ALL_GENERAL_REGS)
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REGS('l', ALL_QLOAD_REGS)
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REGS('s', ALL_QSTORE_REGS)
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REGS('S', ALL_QSTORE_REGS & 0x5555) /* even qstore */
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REGS('w', ALL_VECTOR_REGS)
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/*
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* Define constraint letters for constants:
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* CONST(letter, TCG_CT_CONST_* bit set)
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*/
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CONST('I', TCG_CT_CONST_ARM)
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CONST('K', TCG_CT_CONST_INV)
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CONST('N', TCG_CT_CONST_NEG)
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CONST('O', TCG_CT_CONST_ORRI)
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CONST('V', TCG_CT_CONST_ANDI)
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CONST('Z', TCG_CT_CONST_ZERO)
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