target/mips: Fix TX79 LQ/SQ opcodes
The base register address offset is *signed*.
Cc: qemu-stable@nongnu.org
Fixes: aaaa82a9f9
("target/mips/tx79: Introduce LQ opcode (Load Quadword)")
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20230914090447.12557-1-philmd@linaro.org>
(cherry picked from commit 18f86aecd6a1bea0f78af14587a684ad966d8d3a)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
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@ -24,7 +24,7 @@
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@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
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@rs ...... rs:5 ..... .......... ...... &r sa=0 rt=0 rd=0
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@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
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@rd ...... .......... rd:5 ..... ...... &r sa=0 rs=0 rt=0
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@ldst ...... base:5 rt:5 offset:16 &i
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@ldst ...... base:5 rt:5 offset:s16 &i
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