qemu/target
Richard Henderson 407e6ce7f1 target/arm: SVE brk[ab] merging does not have s bit
While brk[ab] zeroing has a flags setting option, the merging variant
does not.  Retain the same argument structure, to share expansion but
force the flag zero and do not decode bit 22.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20181226215003.31438-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2019-01-07 15:23:45 +00:00
..
alpha
arm target/arm: SVE brk[ab] merging does not have s bit 2019-01-07 15:23:45 +00:00
cris
hppa
i386 Clean up includes 2018-12-20 10:29:08 +01:00
lm32
m68k
microblaze
mips target/mips: Support R5900 three-operand MADD1 and MADDU1 instructions 2019-01-03 17:52:52 +01:00
moxie
nios2
openrisc
ppc Changes requirement for "vsubsbs" instruction 2018-12-21 09:29:12 +11:00
riscv RISC-V Changes for 3.2, Part 1 2019-01-03 13:26:30 +00:00
s390x
sh4
sparc
tilegx
tricore target/tricore: use float32_is_denormal 2018-12-17 08:25:25 +00:00
unicore32
xtensa