8074365fc7
tlb_helper.c's #ifdef'ry hides a quite simple user-mode implementation of mips_cpu_tlb_fill(). Copy the user-mode implementation (without #ifdef'ry) to tcg/user/helper.c and simplify tlb_helper.c's #ifdef'ry. This will allow us to restrict tlb_helper.c to sysemu. Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210428170410.479308-15-f4bug@amsat.org>
65 lines
2 KiB
C
65 lines
2 KiB
C
/*
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* MIPS TLB (Translation lookaside buffer) helpers.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "exec/exec-all.h"
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#include "internal.h"
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static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
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MMUAccessType access_type)
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{
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CPUState *cs = env_cpu(env);
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env->error_code = 0;
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if (access_type == MMU_INST_FETCH) {
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env->error_code |= EXCP_INST_NOTAVAIL;
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}
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/* Reference to kernel address from user mode or supervisor mode */
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/* Reference to supervisor address from user mode */
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if (access_type == MMU_DATA_STORE) {
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cs->exception_index = EXCP_AdES;
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} else {
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cs->exception_index = EXCP_AdEL;
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}
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/* Raise exception */
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if (!(env->hflags & MIPS_HFLAG_DM)) {
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env->CP0_BadVAddr = address;
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}
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}
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bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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MMUAccessType access_type, int mmu_idx,
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bool probe, uintptr_t retaddr)
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{
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MIPSCPU *cpu = MIPS_CPU(cs);
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CPUMIPSState *env = &cpu->env;
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/* data access */
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raise_mmu_exception(env, address, access_type);
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do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr);
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}
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void mips_cpu_do_interrupt(CPUState *cs)
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{
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cs->exception_index = EXCP_NONE;
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}
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